1. Field of the Invention
The present invention relates to a clock control circuit suitable for a system which requires an internal clock having a constant delay relation to an external clock in an integrated circuit.
2. Related Art Statement
Recently, a computer system sometimes adopts a synchronous memory, such as a synchronous DRAM, in order to fulfill the requirements for faster processing. A memory of a synchronous type is also designed to use a clock, which is synchronized to the system clock of a computer system within the memory.
When a delay occurs between a clock used within a memory (hereinafter referred to as internal clock) and an external clock, such as a system clock, and particularly when the operating speed is high, malfunction is apt to occur in a circuit even when the delay time is small.
Accordingly, a clock control circuit is adopted to synchronize an internal clock signal to an external clock signal. FIG. 1 is a circuit diagram showing a related art on such a clock control circuit. A brief description will be given on the theory with reference to the waveform diagrams in FIGS. 1 and 2.
In FIG. 1, an external clock signal CK, shown in FIG. 2, is inputted to an input terminal 1. This external clock signal CK is taken in through a receiver 2. The receiver 2 outputs an amplified clock signal CLK after waveform shaping of the external clock signal. When a delay time at the receiver 2 is D1, the output clock signal CLK of the receiver 2 turns out to be as shown in FIG. 2. A period of the external clock signal CK is supposed to be xcfx84. Without a clock control circuit, as an output signal of the receiver 2 is used as an internal clock signal, the delay time D1 becomes a synchronization error when synchronization of an external clock signal CK is shortened. In contrast to this, a clock control circuit 9 is designed to generate signals delayed to an external clock signal by two periods of the external clock period by delaying the output clock signal CLK of the receiver 2 by the time (2xcfx84xe2x88x92D1).
That is, a clock control circuit 9, as shown in FIG. 2, first generates pulse FCL which rises after the time A from the rising timing of the output clock signal CLK of the receiver 2. The time from the rising of this pulse FCL to the rising of the next clock signal CLK is, as shown in FIG. 2, the time (xcfx84xe2x88x92A). The clock control circuit 9 finds the same time (xcfx84xe2x88x92A) as the time (xcfx84xe2x88x92A), and generates a rearward pulse RCL, shown in FIG. 2, after the time 2(xcfx84xe2x88x92A) from the rising of pulse FCL. The rearward pulse RCL is amplified by an output buffer 6 to be able to drive an internal circuit, and outputted as an internal clock signal CKxe2x80x2.
As shown in FIG. 2, the time from the rising of the clock signal CLK to the rising of the next pulse RCL is xcfx84xe2x88x92(xcfx84xe2x88x92A)=A. A delay time of the output buffer 6 is supposed to be D2. Consequently, as shown in FIG. 2, the clock signal CLK, which has been delayed by the receiver 2 by the time D1 to the external clock signal CK is outputted after being further delayed by the time A by a delay monitor 3, by the time 2(xcfx84xe2x88x92A) by forward-pulse and rearward-pulse delay lines 4 and 5, and by the time D2 by the output buffer 6.
Consequently, a delay of an internal clock signal to an external clock signal becomes 2xcfx84, and the internal clock signal and the external clock signal are synchronized.
This circuit requires a pulse having an external clock signal whose pulse width is narrower than A. When a period of an external clock signal becomes small and A correspondingly becomes small, pulse must be generated to have narrower width, and operation in high frequency becomes difficult.
Hereinafter, configuration, operation and problem of circuits of the related art will be described in detail.
First, description will be given on function and configuration of each part. As a delay time given by the receiver 2 and the output buffer 6 can be found beforehand, it is possible to prepare the delay monitor 3 having a delay time A to be A=D1+D2, as shown in FIG. 2.
In FIG. 1, the delay monitor 3 is a device to obtain this delay time A. The delay monitor 3 is designed to generate forward pulse FCL, which is the clock signal CLK from the receiver 2 delayed by the delay time A, and to output it to a forward-pulse delay line 4. The delay time A is set to a value larger than the pulse width of the clock signal CLK. The forward-pulse delay line 4 is for obtaining a delay time (xcfx84xe2x88x92A), and a rearward-pulse delay line 5 is also for obtaining a delay time (xcfx84xe2x88x92A). As is described later it is designed so that rearward pulse RCL, the output of the rearward-pulse delay line 5, is one delayed by D1+A+2(xcfx84xe2x88x92A) to the external clock signal and further delayed by the time D2 by the output buffer 6 to be outputted as an internal clock signal CKxe2x80x2.
That is, the external clock signal CK inputted through the input terminal 1 is outputted from the output buffer 6, being delayed by D1+A+2(xcfx84xe2x88x92A)+D2. When the delay time A of the delay monitor 3 is set to D1+D2, an internal clock signal CKxe2x80x2, which is synchronized by being delayed by 2xcfx84 to the external clock signal CK, is obtained from the output buffer 6.
The forward-pulse delay line 4 is composed of a plurality of cascaded forward-pulse delay circuits 4-1, 4-2, . . . Each of the forward-pulse delay circuits 4-1, 4-2, . . . is configured with an AND circuit of a NAND circuit and an inverter. To an input terminal of each of the forward-pulse delay circuits 4-2, 4-3, . . . , the output of the forward-pulse delay circuits 4-1, 4-2, . . . in the preceding stage is supplied respectively.
The rearward-pulse delay line 5 is composed of a plurality of cascaded rearward-pulse delay circuits 5-1, 5-2, . . . Each of the rearward-pulse delay circuits 5-1, 5-2, . . . is configured with an AND circuit of a NAND circuit and an inverter. To an input terminal of each of the rearward-pulse delay circuits 5-1, 5-2, . . . , the output of the rearward-pulse delay circuits 5-2, 5-3, . . . in the succeeding stage is supplied respectively. Each of the forward-pulse delay circuits 4-1, 4-2, . . . and each of the rearward-pulse delay circuits 5-1, 5-2, . . . are designed to operate with the same delay time respectively.
Output terminals of the forward-pulse delay circuits 4-1, 4-2, . . . are respectively connected to one input terminal of each of control circuits 7-1, 7-2, . . . , each of which forms a control circuit group 7. The control circuits 7-1, 7-2, . . . are configured with NAND circuits, and the clock signal CLK from the receiver 2 is supplied to the other input terminals of the control circuits 1-1, 7-2, . . .
The control circuits 7-1, 7-2, . . . are designed to supply two-input NAND output as control signals not only to the other input terminals of the forward-pulse delay circuits 4-3, 4-4, . . . , but also to the other input terminals of the rearward-pulse delay circuits 5-1, 5-2, . . . To the other input terminals of the forward-pulse delay circuits 4-1, 4-2, . . . in a first and second stages, electric potential at high level corresponding to logical value xe2x80x9c1xe2x80x9d (hereinafter referred to as xe2x80x9cHxe2x80x9d) is applied. It is also designed so that, to the other input terminals of the rearward-pulse delay circuits in the last stage, signals of xe2x80x9cHxe2x80x9d are supplied. Output terminals of the rearward-pulse delay circuit 5-1 in the first stage are connected to the output buffer 6. The output buffer 6 is designed to delay the output of the rearward-pulse delay circuit 5-1 by the delay time D2 and to output it as the internal clock signal CKxe2x80x2.
A delay unit 8 is configured with a forward-pulse delay circuit in the first stage, a control circuit and a delay element for succeeding stage pulse.
Each of the forward-pulse delay circuits 4-3, 4-4, . . . is designed to propagate the output of the forward-pulse delay circuits 4-2, 4-3, . . . in the preceding stage to the next stage by having a control signal of xe2x80x9cHxe2x80x9d inputted respectively. Similarly, each of the rearward-pulse delay circuits 5-1, 5-2, . . . is designed to propagate the output of the rearward-pulse delay circuits 5-2, 5-3, . . . in the succeeding stage to the preceding stage by having a control signal of xe2x80x9cHxe2x80x9d inputted respectively.
Now, the operation of a related art configured in such a manner will be described in detail with reference to the circuit diagram in FIG. 1 and the operation waveform diagram in FIG. 2.
The external clock signal CK shown in FIG. 2 is inputted through the receiver 2. The output clock signal CLK of the receiver 2 is delayed by the time D1 to the external clock signal CK as shown in FIG. 2. This clock signal CLK is supplied to the delay monitor 3 to be further delayed by the time A, and supplied to the forward-pulse delay line 4 as forward pulse FCL shown in FIG. 2.
Before this forward pulse FCL is generated, the clock signal CLK is on a low level corresponding to a logical value xe2x80x9c0xe2x80x9d (hereinafter referred to as xe2x80x9cLxe2x80x9d), and output terminals of the control circuits 7-1, 7-2, . . . becomes xe2x80x9cHxe2x80x9d. As the other input terminals of the forward-pulse delay circuits 4-1, 4-2, . . . are fixed at xe2x80x9cHxe2x80x9d, all the other input terminals of the forward-pulse delay circuits 4-1, 4-2, . . . are at xe2x80x9cHxe2x80x9d, and each of the forward-pulse delay circuits 4-1, 4-2, . . . sequentially propagates inputted forward pulse FCL. In addition, as one of the input terminals of the rearward-pulse delay circuits in the last stage is fixed at xe2x80x9cHxe2x80x9d, in an initial state where no pulse has been inputted yet, all output terminals of the rearward-pulse delay circuits 5-1, 5-2, . . . are at xe2x80x9cHxe2x80x9d.
Thus, forward pulse propagates by the forward-pulse delay line 4 when the clock signal CLK is at xe2x80x9cLxe2x80x9d. When the clock signal CLK is at xe2x80x9cHxe2x80x9d the control circuits 7-1, 7-2, . . . output inverted signals of the output of the forward-pulse delay circuits 4-1, 4-2, . . . as control signals. Consequently, out of the forward-pulse delay circuits 4-1, 4-2, . . . , control signals in a stage where the xe2x80x9cHxe2x80x9d part of forward pulse FCL is transmitted become xe2x80x9cLxe2x80x9d, and control signals in a stage where the xe2x80x9cLxe2x80x9d part is transmitted become xe2x80x9cHxe2x80x9d.
By supplying this control signal xe2x80x9cLxe2x80x9d to a forward-pulse delay circuit where a forward pulse at xe2x80x9cHxe2x80x9d was inputted, the output of all the forward-pulse delay circuits 4-3, 4-4, . . . in and after the third stage is initialized at xe2x80x9cLxe2x80x9d. Accordingly, a time for forward pulse to propagate by the forward-pulse delay line 4 is a time from the rising of the forward pulse FCL to the rising of the next clock signal CLK, that is, as shown in FIG. 2, the time (xcfx84xe2x88x92A).
Actually, a little delay time exists during a time from the rising timing of the clock signal CLK until the control signal changes. Accordingly, by supplying control signals prepared by a control circuit 7-n in the n-th stage to a forward-pulse delay circuit in the (n+x)th stage, this delay time is offset and all the forward-pulse delay circuits can be initialized. FIG. 1 shows an example where x=2.
The number of stages of a forward-pulse delay circuit, which propagated an output corresponding to the rising edge of forward pulse FCL (P1 part in FIG. 2), corresponds to the time (xcfx84xe2x88x92A). An example of a related art shown in FIG. 1 is designed so that a rearward pulse is generated by a rearward-pulse delay circuit at the rising timing of the clock signal CLK, made propagate by the rearward-pulse delay line 5 by the rising edge of rearward pulse by the time (xcfx84xe2x88x92A), then supplied to the output buffer 6. Accordingly, an output corresponding to the rising edge of rearward pulse generated by a rearward-pulse delay circuit (part P2 in FIG. 2) is also generated at a rearward-pulse delay circuit in a number of stages corresponding to the time (xcfx84xe2x88x92A).
That is, a control signal by the control circuit 7-n in the n-th stage is supplied to the delay element 5-n for rearward pulse in the n-th stage. Out of the rearward-pulse delay circuits 5-1, 5-2, . . . , the output of rearward-pulse delay circuits in a stage where the control signal became xe2x80x9cLxe2x80x9d is changed from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d. In other words, at rising timing of the clock signal CLK, the output of a rearward-pulse delay circuit corresponding to a forward-pulse delay circuit, which outputted a forward pulse at xe2x80x9cHxe2x80x9d, becomes xe2x80x9cLxe2x80x9d. That is, at rising timing of the clock signal CLK, the stage of a forward-pulse delay circuit to output xe2x80x9cHxe2x80x9d correspondingly to the rising edge of the forward pulse coincides with the stage of a rearward-pulse delay circuit to output xe2x80x9cHxe2x80x9d correspondingly to the rising edge of the rearward pulse.
After the forward-pulse delay line 4 is initialized to xe2x80x9cLxe2x80x9d, by xe2x80x9cHxe2x80x9d of the clock signal CLK, control signals in all stages become xe2x80x9cHxe2x80x9d until forward pulse at xe2x80x9cHxe2x80x9d is inputted. With this, rearward pulse propagates from one rearward-pulse delay circuit to another until, after the time (xcfx84xe2x88x92A) from generation of rearward pulse, is outputted from the rearward-pulse delay circuit 5-1, whose rising edge of the rearward pulse RCL is in the first stage (FIG. 2).
The output of the rearward-pulse delay circuit 5-1 is delayed by the output buffer 6 by the time D2, and outputted as the internal clock signal CKxe2x80x2 (FIG. 2).
Delay time of the internal clock signal CKxe2x80x2 to the external clock signal CK is, as shown in FIG. 2:
D1+A+2(xcfx84xe2x88x92A)+D2xe2x80x83xe2x80x83(1)
As the delay time A of the delay monitor 3 is set to be A=D1+D2, the above expression (1) goes as follows:
D1+(D1+D2)+2(xcfx84xe2x88x92D1xe2x88x92D2)+D2=2xcfx84
Thus, delay time of the internal clock signal CKxe2x80x2 to the external clock signal CK can be 2xcfx84, synchronization is established between the external clock signal CK and the internal clock signal CKxe2x80x2.
Now, a description will be given on problems which arise from related arts. In the example of a related art in FIG. 1, operation becomes abnormal when the pulse width of the external clock signal CK is larger than the delay time A of the delay monitor 3. FIGS. 3 and 4 illustrate these problems.
Suppose that an external clock signal CK, whose pulse width is larger than A, is inputted as shown in FIG. 4. This external clock signal CK is delayed by the receiver 2 by the time D1, and supplied to the delay monitor 3. The delay monitor 3 delays the clock signal CLK from the receiver 2 by the time A, and outputs forward pulse FCL.
As the pulse width of the clock signal CLK is larger than A, as shown in FIG. 4, the clock signal CLK is always at xe2x80x9cHxe2x80x9d at rising timing of forward pulse FCL. FIG. 3 shows logical levels of each part in this case.
That is, as the other input terminals of forward-pulse delay circuits 4-1, 4-2 in the first and the second stages are fixed at xe2x80x9cHxe2x80x9d, they always propagate inputted signals. Accordingly, the forward pulse at xe2x80x9cHxe2x80x9d propagates up to the forward-pulse delay circuit 4-3 in the third stage unconditionally. That is, the output of the forward-pulse delay circuits 4-1, 4-2 in the first and the second stages is xe2x80x9cHxe2x80x9d. As the clock signal CLK is also xe2x80x9cHxe2x80x9d, a control signal from the control circuits 7-1, 7-2 in the first and the second stages becomes xe2x80x9cLxe2x80x9d.
Consequently, the output of the forward-pulse delay circuits 4-3, 4-4, . . . in and after the third stage, which are controlled by the control circuits 7-1, 7-2, . . . , becomes xe2x80x9cLxe2x80x9d. In other words, when the clock signal CLK is xe2x80x9cHxe2x80x9d, the forward pulse does not propagate by the forward-pulse delay line 4.
In this case, propagation of forward pulse is started by the clock signal CLK""s becoming xe2x80x9cLxe2x80x9d. In this case, too, the rising of the next clock signal CLK stops propagation of forward pulse. Consequently, as shown in FIG. 4, at rising edge of forward pulse FCL, propagation is impossible for the time (xcfx84xe2x88x92A).
As the propagation time is the same for both the rising edge of rearward pulse and for the rising edge of forward pulse, the time from the rising edge of forward pulse to the output of the rising edge of rearward pulse is forced to be shorter than (xcfx84xe2x88x92A). As a result, as shown in FIG. 4, it becomes impossible to generate an internal clock signal CKxe2x80x2 synchronized with an external clock signal CKxe2x80x2.
To cope with this problem, addition of a pulse generating circuit is considered in order to reduce pulse width of the clock signal CLK. FIGS. 5-7 are block diagrams to show such examples. In FIGS. 5-7, in order to simplify diagrams; signal lines to supply control signals from the control circuit 7 to the forward-pulse delay circuits 4-3, 4-4, . . . are not shown.
FIG. 5 shows an example where the output of a pulse generating circuit 11 is supplied to the delay monitor 3 and the control circuits 7-1, 7-2, . . . , and FIG. 6 shows an example where the output of the pulse generating circuit 11 is supplied to the control circuits 7-1, 7-2, . . . FIG. 7 shows an example where the output of the pulse generating circuit 11 is supplied to the delay monitor 3. This circuit operates when the delay time A at the delay monitor 3 is larger than the pulse width of the output signal CLK of the receiver 2.
The pulse generating circuit 11 is designed to generate a clock signal from the inputted clock signal CLK with a pulse width narrower than A. With this, the control circuits 7-1, 7-2, . . . are controlled with pulse having a width narrower than A. Thus, when input is xe2x80x9cHxe2x80x9d at the control circuits 7-1, 7-2, . . . , forward pulse is prevented from being inputted to the forward-pulse delay line 4, enabling the rising edge of forward pulse to be propagated for the time (xcfx84xe2x88x92A).
However, recent computer systems have become fast operative and external clock frequencies are very high. That is, as the period xcfx84 of an external clock signal is extremely short, the delay time A is set to a very small value by the delay monitor 3. Accordingly, it is highly difficult to generate pulse signals whose width is narrower than the delay time A of the delay monitor 3 even when pulse with wide width is inputted as an external clock signal.
Meanwhile, the circuit in FIG. 1 generates an internal clock signal CKxe2x80x2 synchronized with an external clock signal CK by propagating forward pulse for the time (xcfx84xe2x88x92A) by the forward-pulse delay line 4. However, the time to propagate by the forward-pulse delay line 4 is determined by a delay time of the forward-pulse delay circuits 4-1, 4-2, . . . In the circuit in FIG. 1, as the forward-pulse delay circuits 4-1, 4-2, . . . and the rearward-pulse delay circuits 5-1, 5-2, . . . are configured with two gates of AND circuits, the delay time is relatively large, and error in propagation time of forward pulse is comparatively large. Therefore, its synchronization accuracy is low.
Thus, related art of the clock control circuit has problems: of that it needs to use pulse having very narrow width for control in order to response to high-frequency operation, limiting operating frequency band in high frequency. In addition, the delay time of delay elements for forward and rearward pulse is comparatively long and synchronization accuracy is low.
An object of the present invention is to provide a clock control circuit which enlarges an operating frequency band in high frequency.
Another object of the present invention is to provide a clock control circuit which improves synchronization accuracy.
A clock control circuit according to the present invention comprises a forward-pulse delay line which is configured by cascading delay elements in a predetermined number of stages, a rearward-pulse delay line which is configured by cascading delay elements in a predetermined number of stages, an input device for taking in a first clock signal from the exterior and outputting a second clock signal which is delayed as much as a first delay time from said first clock signal, a forward-pulse generating device for generating a forward pulse by delaying said second clock signal as much as a second delay time, a pulse generating device for generating a control pulse, which is synchronized with said second clock signal, giving permission for said forward pulse inputted to said forward-pulse delay line to be propagated by showing a high level or a low level, and setting the level of said control pulse to said level to permit propagation at the timing where the edge of said forward pulse is inputted to said forward-pulse delay line, a control device for giving said forward pulse to said forward-pulse delay line, permitting propagation of said forward pulse when said control pulse is on a high level or a low level, and delaying it up to timing, which corresponds to the edge of said control pulse, and at the same time, generating rearward pulse in a stage of said rearward-pulse delay line, which corresponds to the stage where said forward pulse was propagated at timing corresponding to the edge of said control pulse, and propagating the generated rearward pulse by said rearward-pulse delay line and outputting it, and an output device for outputting a third clock signal, which is synchronized with said first clock signal by delaying rearward pulse outputted from said rearward-pulse delay line as much as a third delay time.
A clock control circuit according to the present invention also comprises a receiver for taking in a first clock signal from the exterior and outputting a second clock signal which is delayed as much as a first delay time from said first clock signal, a forward-pulse generating circuit for generating forward pulse by delaying said second clock signal as much as a second delay time, a pulse generating circuit for generating a control pulse which is synchronized with said second clock signal and has a pulse duration with the same time width as said second delay time, a forward-pulse delay line which is configured by cascading delay elements in a predetermined number of stages, a rearward-pulse delay line which is configured by cascading delay elements in a predetermined number of stages, a control apparatus for giving said forward pulse to said forward-pulse delay line, permitting said forward pulse to be propagated during the time other than the pulse duration of said control pulse to delay it up to timing which corresponds to edge of said control pulse, and at the same time, generating rearward pulse in a stage of said rearward-pulse delay line which corresponds to the stage where said forward pulse was propagated at the timing corresponding to edge of said control pulse, propagating the generated rearward pulse by said rearward-pulse delay line and outputting rearward pulse, and an output buffer for delaying rearward pulse outputted from said rearward-pulse delay line as much as a third delay time, and outputting a third clock signal which is synchronized with said first clock signal.
A clock control circuit according to the present invention also comprises a forward-pulse delay line wherein delay elements, which are configured with one-gate circuits, are cascaded in a predetermined number of stages, a rearward-pulse delay line wherein delay elements, which are configured with one-gate circuits, are cascaded in a predetermined number of stages, an input means for taking in a first dock signal from the exterior and outputting a second clock signal which is delayed as much as a first delay time from said first clock signal, a control means which gives forward pulse generated by delaying said second clock signal as much as a second delay time to said forward-pulse delay line in order to propagate it and to delay it up to timing corresponding to edge of said second clock signal, and at the same time, generates rearward pulse in a stage of said rearward-pulse delay line corresponding to the stage where said forward pulse was propagated at timing corresponding to edge of said second clock signal, propagates the generated rearward pulse by said rearward-pulse delay line and outputs rearward pulse, and an output means which delays rearward pulse outputted from said rearward-pulse delay line as much as a third delay time, and outputs a third clock signal synchronized with said first clock signal.
A clock control circuit according to the present invention also comprises a forward-pulse delay line whose delay elements are cascaded in a predetermined number of stages, a rearward-pulse delay line whose delay elements are cascaded in a predetermined number of stages, a first input means for taking in a first clock signal from the exterior and outputting a second clock signal delayed as much as a first delay time from this first clock signal, a second input means for outputting a fourth clock signal which is delayed as much time as a second delay time to a third clock signal from the exterior, a control means for giving pulse based on one of said second and fourth clock signals to said forward-pulse delay line, propagates it, delays it up to timing corresponding to edge of the other clock signal, and at the same time, generating rearward pulse in a stage of said rearward-pulse delay line corresponding to the stage where said pulse based on one of the clock signals was propagated at timing corresponding to edge of said the other clock signal, propagating the generated rearward pulse by said rearward-pulse delay line, and outputting rearward pulse, and an output means for delaying rearward pulse outputted from said rearward-pulse delay line as much as a third delay time, and outputting an output clock signal wherein at least either phase or frequency is different from that of said third clock signal as much as a relation based on a mutual relation between said first and third clock signals.
A clock control circuit according to the present invention also comprises a forward-pulse delay line wherein delay elements are cascaded in a predetermined number of stages, a rearward-pulse delay line wherein delay elements are cascaded in a predetermined number of stages, a first input means for taking in a first clock signal from the exterior and outputting a second clock signal which is delayed as much as a first delay time from this first clock signal, a second input means for taking in a third clock signal from the exterior, a control means which gives pulse based on said second clock signal to said forward-pulse delay line, propagates and delays it up to timing corresponding to edge of said third clock signal, and at the same time, generates rearward pulse in a stage of said rearward-pulse delay line corresponding to the stage where pulse based on said second clock signal was propagated at timing corresponding to edge of said third clock signal propagates the generated rearward pulse by said rearward-pulse delay line, and outputs rearward pulse, and an output means which delays rearward pulse outputted from said forward-pulse delay line as much as a third delay time, and outputs an output clock signal wherein at least either phase or frequency is different from that of said third clock signal as much as a relation based on a mutual relation between said first and third clock signals.
Other features and advantages of the present invention will become apparent from the following description.